ReMeCo:Reliable Memristor-Based in-Memory Neuromorphic Computation

Memristor-based in-memory neuromorphic computing systems promise a highly efficient implementation of vector-matrix multiplications, commonly used in artificial neural networks (ANNs). However, the immature fabrication process of memristors and circuit level limitations, i.e., stuck-at-fault (SAF), IR-drop, and device-to-device (D2D) variation, degrade the reliability of these platforms and thus impede their wide deployment. In this paper, we present ReMeCo, a redundancy-based reliability improvement framework. It addresses the non-idealities while constraining the induced overhead. It achieves this by performing a sensitivity analysis on ANN. With the acquired insight, ReMeCo avoids the redundant calculation of least sensitive neurons and layers. ReMeCo uses a heuristic approach to find the balance between recovered accuracy and imposed overhead. ReMeCo further decreases hardware redundancy by exploiting the bit-slicing technique. In addition, the framework employs the ensemble averaging method at the output of every ANN layer to incorporate the redundant neurons. The efficacy of the ReMeCo is assessed using two well-known ANN models, i.e., LeNet, and AlexNet, running the MNIST and CIFAR10 datasets. Our results show 98.5% accuracy recovery with roughly 4% redundancy which is more than 20× lower than the state-of-the-art.</p

Enhancing the Efficiency of Cluster Voltage Scaling Technique for Low-Power Application

Abstract — In this paper, a scheme for power reduction based on Cluster Voltage Scaling (CVS) for gate-level design of the VLSI circuits is presented. To increase the power reduction efficiency of the previous CVS techniques, a new low power level-shifter is utilized in the circuit. In addition, the concept of transistor ordering has been used to further reduce the power consumption. This technique shows an average improvement of 7 % compared to the previous CVS circuits. The impact of CVS and its modified version on the reduction of short-circuit and leakage power are also discussed. I

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies

a b s t r a c t In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on /I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal high write and read margins, the highest I on /I off ratio, a fast write, and ultra-low leakage power in the hold &quot;0&quot; state for the cell. Therefore, the suggested 7T cell may be considered as one of the better design choices for both high performance and low power applications. Also, the changes of cell parameters when the temperature rises from À40 1C to 100 1C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell in the presence of the process variations are studied at two supply voltages of 400 mV and 500 mV. The study shows that the proposed cell meets the required cell sigma value (6σ) under all conditions

Simultaneous power control and power management algorithm with sector-shaped topology for wireless sensor networks

In this paper, we propose a topology control technique to reduce the energy consumption of wireless sensor networks (WSNs). The technique makes use of both power control and power management methods. The algorithm uses the power management technique to put as many idle nodes as possible into the sleep mode while invoking the power control method to adjust the transmission range of the active nodes. On the contrary to earlier works in which both of these methods were used separately, in this algorithm, they are utilized simultaneously to decide about the sleep nodes and the ranges of active nodes. It is an approximation algorithm which is called simultaneous power control and power management algorithm (SPCPM). The performance bound of this centralized algorithm is determined analytically. Then, to make the proposed method practical for WSNs, a distributed algorithm based on SPCPM is introduced. To assess the efficiency of the proposed algorithm, we compare its average energy consumption with those of three existing topology control algorithms for a sector-based WSN. The simulation results which were obtained for different numbers of transmitting sensor nodes reveal less average energy consumptions for SPCPM compared to other algorithms.Peer reviewe

Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits

In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared with those of silicon on insulator-FinFET (SOI-FinFET) and Bulk-FinFET structures (where the BOX layer covers all the regions except the channel region). In addition, we compare different characteristics of static random access memory (SRAM) cells based on the proposed device structure as well as SOI-FinFET and Bulk-FinFET structures. The characteristics include standby power consumption, and read static noise margin (SNM). Finally, the behavior of the proposed device in the presence of dimensional variations (channel length and thin film thickness variations) and random dopant fluctuation (RDF) are studied and compared with those of the other two structures. (C) 2012 Elsevier B.V. All rights reserved